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lds8866 ? 2008 leadis technology 1 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice 6 - channel ultra low dropout led driver features o c harge pump modes : 1 - x , 1.33 - x , 1.5 - x , 2 - x o ultra low dropout powerlite ? current regulator* o drives up to 6 leds up to 3 2 ma each o factory preset current value for each led bank o pwm brightness control with up to 25,000:1 dimming range at 200 hz o power efficiency up to 9 4 % o low input noise & ripple in all charge pump modes o low current shutdown mode o short circuit current limiting o thermal shutdown protection o available in 3 x 3 x 0.8 mm 16 - pin tqfn package appl ication o keypad and display backlight o cellular phones o digital still cameras o pdas and smartphones description the lds 8866 is a high efficiency multi - mode fractional charge pump with ultra low dropout voltage that can drive up to six leds . inclusion of a 1.3 3 - x fractional charge pump mode and ultra low dropout powerlite ? current regulator (pcr) increases device? efficiency up to 9 4 %. new mode requires no additional external capacitors. the pwm1/pwm2 logic input s function as a chip enable and a pwm mode led b rightness control . pwm1 pin contorls leda and ledb banks with four leds , while pwm2 controls bank ledc with two leds . the maximum leds current is factory preset . every led bank with two leds each is program mable separately in the range from 0.5 to 32 ma i n 0.5 ma steps. low noise input ripple is achieved by operating at a constant switching frequency which allows the use of small external ceramic capacitors. the multi - fractional charge pump supports a wide range of input voltages from 2. 7 v to 5.5 v. the device is available in a 16 - lead tqfn 3 mm x 3 mm package with a max height of 0.8 mm. typical application circuit
lds8866 ? 2008 le adis technology 2 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice absolute maximum rat ings parameter rating unit v in , ledx, c1, c2 voltage 6 v v out voltage 6 v pwm1, pwm2 voltage v in + 0.7v v storage temperature range - 65 to +160 c junction temperature range - 40 to +125 c soldering temperature 300 c recommended operatin g conditions parameter rating unit v in 2. 7 to 5.5 v ambient temperature range - 40 to +85 c electrical operating cha racteristics (over recommended operating conditions unless specified otherwise) v in = 3.6v, cin = cout = 1 f, c1 = c2 = 0.22 f, en = high, t amb = 25c name conditions min typ max units quiescent current 1 - x mode 1 . 7 2.5 ma shutdown curren t pwm1 = pw m2 = 0v 1 a led current accuracy to factory preset value - 5 3 +5 % led channel matching (i led - i ledavg ) / i ledavg - 5 3 +5 % 1 - x mode 0.8 1.33 - x mode 3.5 1.5 - x mode 5.5 output resistance (open loop) 1 2 - x mode 6.5 1.33 - x 0.8 charge pump frequency 1.5 - x mode and 2 - x mode 1.1 mhz output short circuit current limit v out < 0.5v 35 ma 1 - x to 1.33 - x , 1.33 - x to 1.5 - x , o r 1.5 - x to 2 - x mode transition threshold 75 130 mv 1.33 - x to 1 - x mode transition hysteresis 6 00 mv charge pump transition filter delay 1 800 s input leakage - 1 1 a high 1.3 pwm1, pwm2 pins logic level low 0.4 v pwm frequency 1 100 10 0 0 00 hz pwm pulse high/low state 200 ns pwm low time to shutdown 30 ms thermal shutdown 1 150 thermal hysteresis 1 20 c v in under v oltage l ockout (uvlo) 2 t hreshold 2. 2 v v out over voltage protection 1 6.2 v 1 sample test only
lds8866 ? 2008 leadis technology 3 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice pin description pin # name function 1 ledc2 ledc2 cathode terminal 2 ledc1 ledc1 cathode terminal 3 ledb2 ledb2 cathode terminal 4 ledb1 ledb1 cathode terminal 5 leda2 leda2 cathode terminal 6 le da1 leda1 cathode terminal 7 v out charge pump output connected to the led anodes 8 v in charge pump input, connect to battery or supply 9 c1+ bucket capacitor 1 positive terminal 10 c1 - bucket capacitor 1 negative terminal 11 c2+ bucket capacitor 2 positive terminal 12 c2 - bucket capacitor 2 negative terminal 13 pwm 2 led c bank pwm brightness control 14 pwm1 led a and l e d b banks pwm brightness control 15 , 16 gnd c onnect both pins to gnd top view: tqfn 16 - lead 3 x 3 mm tab tab bottom thermal pad; connect to gnd on the pcb pin function v in is the supply pin for the charge pump. a small 1 f ceramic bypass capacitor is required between the v in pin and ground near the device. the operating input voltage range is from 2. 7 v to 5.5 v. whenever the input supply falls below the under - voltage threshold ( 2.2 v), all the led channels are disabled, and the device enters shutdown mode. pwm1, pwm2 are the enable and pwm led brightness control logic input s . guaranteed levels of logic high and logic low are set at 1.3 v and 0.4 v respectively. when any of pwm pins is taken high, the device becomes enable d with maximum led current at associated bank . to place the device into zero current mode, both pwm pin s must be held low for more than 30 ms. v out is the charge pump output that is connected to the led anodes. a small 1 f ceramic bypass capacitor is required between the v out pin and ground near the device. gnd is the ground reference for the charge pump. the pin must be connected to the ground plane on the pcb. c1+, c1 - are connected to each side of the ceramic bucket c apacitor c1 c2+, c2 - are connected to each side of the ceramic bucket capacitor c2 led a 1 ? led c2 provide the internal regulated current source for each of the led cathodes. these pins enter high - impedance zero current state whenever the device is in shutdo wn mode. tab is the exposed pad underneath the package. for best thermal performance, the tab should be soldered to the pcb and connected to the ground plane
lds8866 ? 2008 le adis technology 4 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice typical characterist ics vin = 3.6v, i out = 1 8 0ma (6 leds at 3 0ma), c 1 = c 2 = 0.22 f , c in = c out = 1 f, t amb = 25c unless otherwise specified power efficiency vs. input voltage at v f = 3.2 v power - up in 1 - x mode ch1 ? pwm, pwm2 , ch2 ? vout, ch3 ? output current (100ma/div) power - up in 1.33 - x mode ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div) power - up in 1.5 - x mode ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div) power - up in 2 - x mode ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div) power - down delay ( 1 - x mod e) ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div)
lds8866 ? 2008 leadis technology 5 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice typical characterist ics vin = 3.6v, i out = 1 8 0ma (6 leds at 3 0ma), c 1 = c 2 = 0.22 f , c in = c out = 1 f, t amb = 25c unless otherwise specified operating waveforms at 1khz pwm mode ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div) operating waveforms at 10khz pwm mode ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div) operating waveforms at 50khz pwm mode ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div) operating waveforms at 100khz pwm mode ch1 ? pwm 1 , pwm2 , ch2 ? vout, ch3 ? output current (100ma/div)
lds8866 ? 2008 le adis technology 6 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice block diagram figure 2. lds 88 66 functional block diagram basic operation at power - up , pwm1 and pwm2 pins should be logic low. during power - up device performs internal circuits reset that requires less than 10s. to start device either pwm1 or pwm2 pin should be set logic high 10 s after than input voltage applied. device st arts operating at 1 - x mode a t which the output is approximately equal to the input supply voltage (less any internal voltage losses). if the output voltage is sufficient to regulate all led currents, the device re mains in 1 - x operating mode. the low dropout powerlite ? current regulator (pcr) performs well at input voltages vin up to 75 mv above led forward voltage v f significantly increasing driver?s efficiency. the lds8866 monitors voltage drop vd across pcr at every channel in on state. if this voltage falls below 7 5 mv (typical) at any one channel, (channel with led with highest forward voltage), the mode control block changes charge pump mode to the next multiplication ratio. vd = v in x m ? v f ? rcp x iout, where rcp is a charge pump output resistance at given mode , iout is sum of all led currents, and m is a charge pump? multiplication ratio. if the input voltage is insufficient or falls to a level where vd 75 mv, and the regulated currents cannot be maintained, the low dropout powerlite ? current regulator switches the charge pump into 1.33 - x mode (after a fixed delay time of about 8 00 s). in 1.33 - x mode, the charge pump? output voltage is approximately eq ual to 1.33 times the input supply voltage (less any internal voltage losses). this sequence repeats at every mode until driv er enters the 2 - x mode. if the device detects a sufficient input voltage is present to drive all led currents in 1 - x mode, it will change automatically back to 1 - x mode. this only applies for changing back to the 1 - x mode. the
lds8866 ? 2008 leadis technology 7 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice difference between the input voltage when exiting 1 - x mode and returning to 1 - x mode is called the 1 - x mode transition hysteresis (about 6 00 mv ) . operation of pwm - based led current control the maximum current value in each of the lds8866?s three led banks is factory preset; to set each iled below this value , a pwm (a duty cycle based) control signal can be applied at the pwm1/pwm2 pins. using a pwm control tech nique guarantees stable wled color temperature over a wide range of led currents. the led color temperature set at the factory preset maximum led current does not vary with respect to the average led current unlike conventional 1 - wire led current control m ethods. the lds8866 ?s pwm logic control circuits have been designed to operate from 100 hz to 100 khz with duty cycle s higher than (0.02*f)% and lower than (100 ? 0.02*f)%, where f is the pwm control frequency in khz. the brightness dynamic dimming range a t 200 hz is 25,000 : 1. pwm control frequencies l ower than 100 hz are not recommended ( especial l y with short duty cycles ) because led flicker may become visible. when pwm current control is enabled, the led current is modulate d from zero to 100% over a sin gle pwm period. for example, when pwm1/pwm2 is logic high, the led current is set equal to the maximum factory preset value . when pwm1/pwm2 is logic low , the led current is zero. the average led curr ent level is then determined by the pwm duty cycl e that m ay be adjusted as described above. figure 3. lds8866 timing diagram note: timing diagram represents condition when led forward voltage vf is higher than charge pump mode times (1.5) input voltage minus voltage drop on current regulator v pcr and minus vol tage drop on charge pump output resistance rcp at iled current through n leds. vf > cpm x vin ? vd ? rcp x iled x n ; pwm duty cycle = t pwm on / (t pwm on + t pwm off ) when led current control is enabled at the pwm1/pwm2 inputs , the lds8866?s maximum inpu t current is determined by the factory preset maximum led current multiplied by number of led used, the charge pump operating mode ( 1 - x , 1.33 - x , 1.5 - x , or 2 - x ) , and divided by charge - pump driver?s efficiency. for example, i f six leds are used and the charg e pump is operating in 2 - x mode, the maximum pulse current at v in would then be 400 ma ( = 30 ma /led x
lds8866 ? 2008 le adis technology 8 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice 6 leds x 2 /0.9 ) , assuming that charge pump ?s efficiency alone at 2 - x mode is 90% and maximum factory preset current is 30 ma per led . when pwm led current control is first enabled (a t cold start, for example) , the lds8866?s v in , v out , and v pcr monitors cause the lds8866?s charge pump to cycle through all four operating modes (if necessary) so that v out is high enough to maintain regulated led current. to pr event nuisance switching of the charge pump during this initial start - up sequence, a 0.8ms transition filter is applied at each charge - pump mode. depending on v in and the v f of the leds chosen, the maximum cold - start delay to regulated led current operatio n can be up to 2.4ms. (see timing diagram figure 3) once the lds8866 reaches steady - state operation, its charge pump remains in operation even when the led current is turned off (t off ). as shown in figure 3 , v out increases slightly by an amount proportiona l to the voltage drop generated by charge pump? s r out and the total led current load. the lds8866?s efficiency and led current regulation are not affected because the leds are off during this time. if the pwm1/pwm2 pins are held high or low longer than 30m s (time to shutdown), the lds8866 turns leds off. if pwm1/pwm2 pins are low, shutdown mode is enabled and the supply current drops to 1 a or less. if pwm1/pwm2 pins are logic high , the lds8866 charge pump remains active with an overall quiescent current ~ 1 ma. unused led channels for applications with only two or four leds, unused led banks can be disabled via the appropriate pwm pin connected to the ground. for applications requiring 1, 3, or 5 channels, the unused led pins should be tied to v out (see fi gure 4 ). if led pin voltage is within 1 v of v out , then the channel is switched off and a 2 5 0 a test current is placed in the channel to sense when the channel moves below v out ? 1 .5 v. figure 4 . application circuit with 5 leds protection mode s the lds8866 has follow protection modes 1. led short to v out protection if led pin is shorted to v ou t , led burned out becomes as short circuit , or led pin voltage is within from v out to (v out - 1.5v ) range, lds8866 recognizes this condition as ?led short? and disables this channel . if led pin voltage is less than (vout ? 1.5v), lds8866 restores led curre nt at this particular channel to programmed value. 2. v out o ver - v oltage p rotection the charge pump? output voltage v out automatically limits at about 6.2 v maximum. this is to prevent the output pin from exceeding its absolute maximum rating. 3. v out s hort c ircuit p rotection if v out is shorted to ground before lds8866 is enabled , input current may i ncrease up to 200 ? 300 ma within 2 0 s after enable and is limited to 35 ? 40 ma after that . 4. over - t emperature p rotection if the die temperature exceeds +15 0c, the driver will enter shutdown mode. the lds8866 requires restart after die temperature falls below 130 c . 5. input v oltage u nder - voltage l ockout if v in falls below 2.2 v (typical value), lds8866 enters shutdown mode. device requires restart when inpu t voltage rises above 2.3 v. 6. low v in or h igh led v f v oltage detection if , in 2 - x mode, v in is too low to maintain regulated led current for given led v f , or led becomes an open circuit, or if any led at active channels is disconnected, lds8866 starts su bsequently changing modes ( 2 - x ? 1 - x ? 1.33 - x - 1.5 - x ? 2 - x - ?) in an attempt to compensate insufficient voltage. as a result, average current at all other channels that are on may fall below regulated level. led selection leds with forward voltages (v f ) r anging from 1. 6 v to 3. 6 v may be used. charge pumps operate in highest efficiency when v f voltage is close to v in voltage multiplied by switching mode, i.e. v in x 1, v in x 1.33 , and so on . if the power source is a li - ion battery, leds with vf = 2.7 v - 3. 3 v are recommended to achieve highest efficiency performance and extended operation on a single battery charge.
lds8866 ? 2008 leadis technology 9 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice external components the driver requires two external 1 f ceramic capa - citors (x5r or x7r type) for decoupling input, output, and two 0.22 f ceramic capa citors (x5r or x7r type) for the charge pump. in all charge pump modes, the input current ripple is very low , and an input bypass capacitor of 1f is sufficient. in 1 - x mode, the device operates in linear mode and does not introduce switching noise back onto the supply. recommended layout in charge pump mode, the driver switches internally at a high frequency. it is recommended to minimize trace length to all four capacitors. a ground plane should cover the area under the driver ic as well as the bypass capacitors. short connection to ground on capacitors cin and cout can be implemented with the use of multiple via. a copper area matching the tqfn exposed pad (tab) must be connected to the ground plane underneath. the use of multiple via improv es the package heat dissipation. figure 5 . recommended layout
lds8866 ? 2008 leadis t echnology 10 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice package drawing and dimensions 16 - pin tqfn (hv3), 3mm x 3mm, 0.5mm pitch symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a2 0.178 0.203 0.228 b 0. 20 0.2 5 0. 30 d 2.9 5 3.00 3. 05 d1 1. 65 1. 70 1.7 5 e 2.9 5 3.00 3. 05 e1 1. 65 1. 70 1.7 5 e 0.50 typ l 0.3 2 5 0. 375 0.4 25 m 0.150 typ n 0.225 typ note: 1. all d imensions are in millimeters 2. complies with jedec standard mo - 220
lds8866 ? 2008 leadis technology 11 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice ordering information part number package package mark ing lds 8866 002 - t2 300/300/300 tqfn - 16 3 x 3mm 886 6 notes: 1. matte - tin plated finish (rohs - compliant) 2. quantity per reel is 2000 example of ordering information notes: 1) all packages are rohs - compliant (lead - free, halogen - free). 2) the standard lead finish is matte - tin. 3) the device used in the above example is a lds8866 002 ? t2 ( 3x3 tqfn, tape & reel , 3 0 / 25 / 5 ma maximum current per led bank ). 4) for additional package and temperature options, please contact your nearest leadis technology sales offic e. company id package 002 : 3x3 tqfn prefix device # suffix lds 8866 002 t2 3 0 0/ 25 0/ 105 product number tape & reel t: tape & reel 2: 2000/reel leda current 3 0 .0 ma ledb current 25 .0 ma ledc current 10.5 ma current value
lds8866 ? 2008 leadis technology 12 doc. no. 8866ds , rev. 2.0 characteristics subject to change without notice leadis technology 800 w. california ave, suite 200 sunnyvale, ca 94086 phone: 408.331.86 00 document no: 8866ds fax: 408.331.8601 revision: 2.0 http:// www.leadis.com issue date: 12/16/2008 warranty and use leadis technology makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability arising out of any such use or application, including but not limited to, consequential or incidental damages. leadis technology pro ducts are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the leadis technol ogy product could create a situation where personal injury or death may occur. leadis technology reserves the right to make changes to or discontinue any product or service described herein without notice. products with data sheets labeled "advance inform ation" or "preliminary" and other products described herein may not be in production or offered for sale. leadis technology advises customers to obtain the current version of the relevant product information before placing orders. circuit diagrams illustr ate typical semiconductor applications and may not be complete .

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